The present invention is directed to semiconductor devices incorporating junctions of varying conductivity types designed to conduct current and methods of making such devices. More specifically, the present invention is directed to integrated circuitry comprising complementary metal-oxide field-effect transistors (CMOS) vertical replacement-gate (VRG) field-effect transistor devices and methods for fabricating integrated circuits incorporating such devices.
Enhancing semiconductor device performance and increasing device density (the number of devices per unit area), continue to be important objectives of the semiconductor industry. Device density is increased by making individual devices smaller and packing devices more compactly. But, as the device dimensions (also referred to as the feature size or design rules) decrease, the methods for forming devices and their constituent elements must be adapted. For instance, production device sizes are currently in the range of 0.25 microns to 0.18 microns, with an inexorable trend toward smaller dimensions. However, as the device dimensions shrink, certain manufacturing limitations arise, especially with respect to the attendant lithographic processes. In fact, current lithographic processes are nearing the point where they are unable to accurately manufacture devices at the required minimal sizes demanded by today""s device users.
Currently most metal-oxide-semiconductor field effect transistors (MOSFETs) are formed in a lateral configuration, with the current flowing parallel to the plane of the substrate or body surface. As the size of these MOSFET devices decreases to achieve increased device density, the fabrication process becomes increasingly difficult. In particular, the lithographic process for creating the gate channel is problematic, as the wavelength of the radiation used to delineate an image in the lithographic pattern approaches the device dimensions. Therefore, for such lateral MOSFETs, the gate length is approaching the point where it cannot be precisely controlled through the lithographic techniques.
Recent advances in packing density have resulted in several variations of a vertical MOSFET. In particular, the vertical device described in Takato, H., et al., xe2x80x9cImpact of Surrounding Gates Transistor (SGT) for Ultra-High-Density LSI""s, IEEE Transactions on Electron Devices, Volume 38(3), pp. 573-577 (1991), has been proposed as an alternative to the planar or lateral MOSFET device. Recently, there has been described a MOSFET characterized as a vertical replacement gate transistor. See Hergenrother, et al, xe2x80x9cThe Vertical-Replacement Gate (VRG) MOSFETxe2x80x9d A50-nm Vertical MOSFET with Lithography-Independent Gate Length,xe2x80x9d Technical Digest of the International Electron Devices Meeting, p. 75, 1999.
A plurality of planar MOSFET active devices fabricated on an integrated circuit chip are shown in the FIG. 1 cross-sectional view. A substrate 9 comprises a p+ portion 50 and a pxe2x88x92 layer 52, the latter typically grown by an epitaxial technique. MOSFETs 2, 4 and 6 are fabricated on the substrate 9. The MOSFET 2 is separated from the MOSFET 4 by a LOCOS (local oxidation of silicon) region 10. Similarly, the MOSFET 6 is separated from the MOSFET 4 by a LOCOS region 12. Alternatively, the MOSFETS 2, 4 and 6 may be electrically separated by shallow trench isolation (STI) techniques. The MOSFET 2 includes a gate 14, a source region 16 and a drain region 18 diffused in an n-type well 20. The MOSFET 4 includes a gate 28, a source region 30 and a drain region 32 diffused into a p-type well 34. Finally, the MOSFET 6 includes a gate 38, a source region 40 and a drain region 42, diffused in an n-type well 44. The gates 14, 28 and 38 are separated from the substrate 9 by a silicon dioxide layer 46, also referred to as the gate oxide layer. As FIG. 1 (and the other Figures in the present application) is intended to be a simplified representation of a portion of an integrated circuit, the various contacts, interconnects, vias and metal layers are not shown and the features are not drawn to scale.
It is particularly advantageous, especially in digital applications, to fabricate a combination of an n-channel and a p-channel MOSFETs on adjacent regions of a chip. This complementary MOSFET (CMOS) configuration is illustrated in the form of a basic inverter circuit in FIG. 2. The drains of the MOSFETs (for instance the MOSFETs 2 and 4 in FIG. 1) are connected together and form the output. The input terminal is the common connection of the MOSFET gates (for example the gates 14 and 28 of FIG. 1). In the FIG. 2 schematic, the MOSFET 2 is the PMOS device and the MOSFET 4 is the NMOS device illustrated in the FIG. 1 cross-section.
To provide further advances in the use of CMOS semiconductor devices, an architecture is provided for creating vertical replacement gate (VRG) CMOS devices, which offer the advantages of both the ubiquitous CMOS device along with the desirable space-saving and fabrication advancements associated with the VRG device.
According to one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material having first and second spaced-apart and isolated doped regions formed therein, wherein the first and the second doped regions are of opposite conductivity type. A third doped region of a different conductivity type than the first doped region is formed over the first doped region. A fourth doped region is formed over the second doped region with a different conductivity type than the second doped region. First and second oxide layers are formed proximate to the third and fourth doped regions, respectively.
The first doped region is a source/drain region of a first field-effect transistor, and the third doped region is the channel. The source/drain region of a second field-effect transistor comprises the second doped region and the fourth doped region forms the channel thereof. A second source/drain region for each MOSFET is formed over each of the channels.
In an associated method of manufacture, an integrated circuit structure is fabricated by providing a semiconductor layer suitable for device formation and having a surface formed along a first plane. For a first field-effect transistor a first device region is formed in the semiconductor layer, wherein the device region is selected from among a source and a drain region. For a second field-effect transistor a second device region is formed in the semiconductor layer, wherein the second device region is selected from among a source and a drain region and is further isolated from the first device region. Channel regions for each of the first and the second field-effect transistors are formed above the first and the second device regions, respectively, within trenches formed in a plurality of regions over the first and the second device regions. At least two of the plurality of layers comprise doped insulating layers from which source/drain extension regions are formed. A first doped insulating layer of a first conductivity type is formed over the first device region followed by the formation of a doped insulating layer over the entire structure and of the second conductivity type. The second doped insulating layer is then removed in the area overlying the first device region such that the resulting structure comprises the first doped insulating layer over the first device region and the second doped insulting layer over the second device region. Similar processing steps are used to form third and fourth doped insulating layers over the first and the second doped insulating layers, respectively. Disposed between the first/second and the third/fourth doped insulating regions is a sacrificial layer that is later removed to allow the formation of gate oxide material in exposed portions of the channel regions.